SHA-256 hash function calculator
Authors: Astakhov S.V., Varihanov D.I. | |
Published in issue: #8(85)/2023 | |
DOI: 10.18698/2541-8009-2023-8-924 | |
Category: Informatics, Computer Engineering and Control | Chapter: Automation, Control of Technological Processes, and Industrial Control |
|
Keywords: SHA-256, hash function, FPGA, calculator, Verilog, Xilinx, digital circuitry |
|
Published: 27.08.2023 |
The paper presents design of a device that calculates inner cycle of the SHA-256 hashing algorithm. The device makes it possible to calculate the SHA-256 algorithm inner cycle in accordance with the Secure Hash Standard. Hash functions, including the SHA-256, are mainly used to calculate checksums, work with the electronic signature and construct unique identifiers for the data sets. Widespread use of the hash functions in modern information systems determines relevance of this work. During the design, the development object at the functional level was analyzed, the device functional diagram was elaborated, the device description was prepared in the Verilog language, and the device RTL diagram synthesis was performed.
References
[1] Hashimoto Y., Noda S. Pricing of Mining ASIC and Its Implication to the High Volatility of Cryptocurrency Prices. Social Science Research Network. URL: https://papers.ssrn.com/sol3/papers.cfm?abstract_id=3368286 (accessed April 08, 2019).
[2] Dang Q.H. Secure Hash Standard (SHS). Gaithersburg, National Institute of Standards and Technology, 2015, 36 p. https://doi.org/10.6028/NIST.FIPS.180-4
[3] Semashko A.V., Kulakov A.V. Aspects of ensurance the integrity of information using block chain transactions research. Informatsionnye sistemy i tekhnologii. Mater. dokl. XXIV Mezhdunar. nauch.-tekhnich. konf., posv. 100-letiyu Nizhegorodskoy radiolaboratorii: sb. tr. [Information systems and technologies. Proceedings of the XXIV International Scientific and Technical Conference Dedicated to the 100th Anniversary of the Nizhny Novgorod Radio Laboratory]. Nizhniy Novgorod, NNSTU, 2018, pp. 534–538. (In Russ.).
[4] Eastlake D., Hansen T. RFC 4634, US Secure Hash Algorithms. New Jersey, AT&T Labs, 2006, 108 p.
[5] Popov A.Yu. Proektirovanie tsifrovykh ustroystv s ispol’zovaniem PLIS [Designing digital devices using FPGAs]. Moscow, BMSTU Press, 2009, 79 p. (In Russ.).
[6] Uilkinson B. Osnovy proektirovaniya tsifrovykh skhem [Fundamentals of digital circuit design]. Moscow, Vil’yams Publ., 2004, 320 p.
[7] Cong J., Liu B., Neuendorffer S., Noguera J., Vissers K., Zhang Z. High-level synthesis for FPGAs: from prototyping to deployment. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011, vol. 30 (4), pp. 473–491. https://doi.org/10.1109/TCAD.2011.2110592
[8] Spear C. System Verilog for verification. Marlboro, Springer Science, 2008, 425 p.
[9] Razbiraem kazhdyy shag khesh-algoritma SHA-256 [Parsing each step of the SHA-256 hash algorithm]. URL: https://habr.com/ru/companies/selectel/articles/530262/ (accessed June 16, 2023).
[10] Forster C., Mull A., Doehla S., Gerhaeuzer K., Heuberger A. Apparatus and method for transmitting a plurality of information signals in flexible time-division multiplexing. Patent no. US8804768B2, USA, H04J 3/16, 2014, 21 p.