Comparative analysis of efficiency of hardware and program implementation of compression algorithm of video

Authors: Kobetskiy V.A., Kazakov N.D.
Published in issue: #8(25)/2018
DOI: 10.18698/2541-8009-2018-8-360
Category: Informatics, Computer Engineering and Control | Chapter: System Analysis, Control, and Information Processing, Statistics
Keywords: video coding, FPGA, processor system, compression efficiency, video codec scheme, implementation of the video codec, encryption algorithm, video stream compression
Published: 09.08.2018

The article analyzes the running efficiency of various implementations of the video encryption algorithm. The general algorithm of video codec operation is considered. The structural scheme of the video codec and a description of its components are developed. The software implementation of the video codec on the processor system is tested. Testing of the hardware implementation of the video codec on a programmable logic integrated circuit (FPGA) is carried out. In the course of studies, the compression rate of the video stream data for both versions of implementation of the video codec is determined. Comparison of the compression efficiency of the video codec on the FPGA and on the processor system is the result of the article Conclusions about the scope of various implementations of the video codec and the relevance of their development in the future are made.

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